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Department of Electronic Engineering

홈 영문-일반대학원 Department Department of Electronic Engineering Faculty

Name	Jaewon, Nam
MAJOR	Mixed-signal IC Design
TEL	02-970-6478
E-mail	jaewon.nam@seoultech.ac.kr
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Biography

University of Southern California, Ph.D.(Electrical Engineering)

Careers

◾ ETRI, Daejeon, South Korea
- Graduate Intern (2006.Oct. - 2007.Oct)
- Research Staff (2008.Feb. - 2012.June)

◾ Intel Corporation (DCG), Santa Clara CA, US
- Graduate Intern (2017. Oct - 2017. Dec)

◾ Intel Corporation LTD AD, Hillsboro OR, US
- Analog Engineer (2019. Sept - 2020. July)

Research Areas

◾ 모노리식 집적 방식 콜로이드 양자점 기반 이미지 센서 구현 (방사청-고려대-한양대ERICA: 미래도전국방 연구용역)

◾ 확장성, 신뢰성을 갖춘 양자컴퓨터 실현을 위한 극저온 CMOS Interconnect Electronics 연구 (연구재단: 기초연구실지원사업 BRL)

◾ PCIe Gen 6.0급 데이터 전송을 위한 64GT/s CMOS 유선 수신기 IP 개발 (연구재단: 생애첫연구)

◾ 반도체 물리적 복제 불가능 회로를 이용한 하드웨어 기반 경량 인증 정보보안 SoC 개발 (연구재단: 중견연구-참여공동연구)

◾ Mixed-signal Analog Integrated Circuit Design

◾ Data-converter based Wireline Tx & Rx

◾ Cryogenic Sensor Interface ROIC (including CIS)

◾ Hardware Security (SRAM based PUF)

◾ Machine-Learning assisted design automation

Teaching

◾ Electronic Circuits-(1)

◾ Electronic Circuits-(2)

◾ Integrated Circuit Design

◾ Mixed-signal Circuit Design

◾ VLSI Design

Selected Publications

◾ High-speed Light Detection Sensor for Hardware Security in Standard CMOS Technology, IEEE TCAS-II 2023.

◾ AMS Circuit Design Optimization Technique Based on ANN Regression Model with VAE Structure", IEEE Access 2023.

◾ Compact SRAM-based PUF Chip Employing Body Voltage Control Technique, IEEE Access 2022.

◾ A 12.8-Gbaud ADC-based Wireline Receiver with Embedded IIR Equalizer, IEEE JSSC, 2019.

◾ A 12-bit 1.6, 3.2, and 6.4 GS/s 4-b/cycle Time-Interleaved SAR ADC with Dual Reference Shifting and Interpolation, IEEE JSSC, 2018

◾ An embedded passive gain technique for asynchronous SAR ADC achieving 10.2 ENOB 1.36-mW at 95-MS/s in 65 nm CMOS, IEEE TCAS-I, 2016.

Journal Papers

◾ A Reconfigurable SRAM CRP PUF with High Reliability and Randomness, ELECTRONICS, vol.13 No.2 pp.1~13, 2024남재원

◾ Analysis of Quarter Method Applied ROM-Based DDFS Architecture, IEEE ACCESS, vol.11 pp.117137~117148, 2023남재원

◾ High-Speed Light Detection Sensor for Hardware Security in Standard CMOS Technology, IEEE Transactions on Circuits and Systems--II: Express Briefs, vol.70 No.10 pp.3917~3921, 2023남재원

◾ AMS Circuit Design Optimization Technique Based on ANN Regression Model With VAE Structure, IEEE ACCESS, vol.11 pp.58850~58862, 2023
[원문보기] 남재원

◾ CMOS Interconnect Electronics Architecture for Reliable and Scalable Quantum Computer, Journal of IKEEE, vol.27 No.1 pp.12~18, 2023
[원문보기] 남재원

◾ Stochastic Cell- and Bit-Discard Technique to Improve Randomness of a TRNG, Electronics, vol.11 No.11, 2022
[원문보기] 남재원

◾ Compact SRAM-Based PUF Chip Employing Body Voltage Control Technique, ACCESS, vol.10 pp.22311~22319, 2022
[원문보기] 남재원

◾ Regression Model-Based AMS Circuit Optimization Technique Utilizing Parameterized Operating Condition, Electronics, vol.11 No.3, 2022
[원문보기] 남재원

◾ 벌크 실리콘 기판을 이용한 삼차원 선택적 산화 방식의 핀 채널 MOSFET, Journal of convergence for information technology, vol.11 No.11 pp.159~165, 2021
[원문보기] 남재원

◾ A Low-Power Class-C Voltage-Controlled Oscillator with Robust Start-Up and Compact High-Q Capacitor Array, IEEE Transactions on Circuits and Systems II: Express Briefs, 2021
[원문보기] 남재원

◾ 5-bit FLASH A/D Converter Employing Time-interpolation Technique, Journal of convergence for information technology, vol.11 No.9 pp.124~129, 2021
[원문보기] 남재원

◾ 내재된 IIR 필터를 활용한 12.8-Gbaud ADC기반 유선수신기, IEEE Solid-State Circuits Society, vol.55 No.3 pp.557~566, 2020
[원문보기] 남재원

◾ A 12-bit 1.6, 3.2, and 6.4 GS/s 4-b/cycle time-interleaved SAR ADC with dual reference shifting and interpolation, IEEE Solid-State Circuits Society, vol.53 No.6 pp.1765~1779, 2018
[원문보기] 남재원

◾ An embedded passive gain technique for asynchronous SAR ADC achieving 10.2 ENOB 1.36-mW at 95-MS/s in 65 nm CMOS, IEEE Transactions on Circuits and Systems I: Regular Papers, vol.63 No.10 pp.1628~1638, 2016
[원문보기] 남재원

◾ A dual-channel pipelined ADC With sub-ADC based on flash–SAR architecture, IEEE Circuits and Systems Society, vol.59 No.11 pp.741~745, 2012
[원문보기] 남재원

◾ A 10-bit 30-MS/s successive approximation register analog-to-digital converter for low-power sub-sampling applications, Elsevier Microelectronics Jounal, vol.42 No.12 pp.1335~1342, 2011
[원문보기] 남재원

◾ A 12-bit 200-MS/s pipelined A/D converter with sampling skew reduction technique, Elsevier Microelectronics Jounal, vol.42 No.11 pp.1225~1230, 2011
[원문보기] 남재원

◾ A 9-bit 80 MS/s successive approximation register analog-to-digital converter with a capacitor reduction technique, IEEE Transactions on Circuits and System II: Express Briefs, vol.57 No.7 pp.502~506, 2010
[원문보기] 남재원

◾ 이미지 신호처리분야에 적용가능한 1.2 V 12 b 60 MS/s CMOS 아날로그 프론트-엔드, ETRI Journal, vol.31 No.6 pp.717~724, 2009
[원문보기] 남재원

Projects

◾ 모노리식 집적 방식 콜로이드 양자점 기반 이미지 센서 구현 연구용역, 한양대학교 ERICA (연구책임) (2023-07-07 ~ 2025-11-30)

◾ PCIe Gen 6.0급 데이터 전송을 위한 64GT/s CMOS 유선 수신기 IP 개발, 과학기술정보통신부, 한국연구재단 생애첫연구 (연구책임) (2021-03-01 ~ 2024-02-29)

◾ 차세대시스템반도체설계전문인력양성사업, 산업통상자원부, 한국반도체산업협회 인력양성사업 (공동연구) (2021-03.01 ~ 2026-02-28)

◾ AI반도체 프로세싱 소프트웨어 핵심기술 개발, 과학기술정보통신부, 정보통신기획평가원 ITRC 인력양성사업 (공동연구) (2022-07-01 ~ 2029-12-31)

◾ 확장성, 신뢰성 갖춘 양자컴퓨터 실현을 위한 극저온 CMOS Interconnect Electronics 개발, 과학기술정보통신부, 한국연구재단 기초연구실, (공동연구) (2021-09-01 ~ 2024-02-29)

◾ 반도체 물리적 복제 불가능 회로를 이용한 하드웨어 기반 경량 인증 정보보안 SoC 개발, 과학기술정보통신부, 한국연구재단 중견연구 (참여연구) (2021-09-01 ~ 2024-02-29)

◾ 차세대시스템반도체설계전문인력양성사업, 산업통상자원부, 2022.03.~2023.02.남재원