◾ Amorphous BN-Based Synaptic Device with High Performance in Neuromorphic Computing, Materials, vol.16 No.20 pp.6698~, 2023심원보
◾ Effect of interfacial SiO2 layer thickness on the memory performances in the HfAlOx-based ferroelectric tunnel junction for a neuromorphic system, JOURNAL OF MATERIALS CHEMISTRY C, vol.11 No.40 pp.13886~13896, 2023심원보
◾ Design Strategies of 40 nm Split-Gate NOR Flash Memory Device for Low-Power Compute-in-Memory Applications, Micromachines, vol.14 No.9 pp.1753~, 2023심원보
◾ Spiking Neural Network With Weight-Sharing Synaptic Array for Multi-input Processing, IEEE ELECTRON DEVICE LETTERS, vol.43 No.10 pp.1657~1660, 2022심원보
◾ Impact of 3D NAND Current Variation on Inference Accuracy for In-memory Computing, JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, vol.22 No.5 pp.341~345, 2022심원보
◾ GP3D: 3D NAND Based In-Memory Graph Processing Accelerator, IEEE JOURNAL ON EMERGING AND SELECTED TOPICS IN CIRCUITS AND SYSTEMS, vol.12 No.2 pp.500~507, 2022심원보
◾ Temperature-Resilient RRAM-Based In-Memory Computing for DNN Inference, IEEE MICRO, vol.42 No.1 pp.89~98, 2022심원보
◾ A Technology Path for Scaling Embedded FeRAM to 28 nm and Beyond With 2T1C Structure, Transactions on Electron Devices, vol.69 No.1 pp.109~114, 2021심원보
◾ Ferroelectric HfO2-based synaptic devices: recent trends and prospects, SEMICONDUCTOR SCIENCE AND TECHNOLOGY, vol.36 No.10, 2021심원보
◾ RRAM for Compute-in-Memory: From Inference to Training, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, vol.68 No.7 pp.2753~2765, 2021심원보
◾ Ferroelectric field effect transistor based 3D NAND architecture for energy efficient on-chip training accelerator, Journal on Exploratory Solid-State Computational Devices and Circuits, vol.7 No.1 pp.1~9, 2021심원보
◾ System-Technology Co-Design of 3D NAND Flash based Compute-in-Memory Inference Engine, Journal on Exploratory Solid-State Computational Devices and Circuits, vol.7 No.1 pp.61~69, 2021심원보
◾ Impact of Random Phase Distribution in Ferroelectric Transistors based 3D NAND Architecture on In-Memory Computing, Transactions on Electron Devices, vol.68 No.5 pp.2543~2548, 2021심원보
◾ Technological design of 3D NAND based compute-in-memory architecture for GB-scale deep neural network, Electron Device Letters, vol.42 No.2 pp.160~163, 2021심원보
◾ Two-step write-verify scheme and impact of the read noise in multilevel RRAM-based inference engine, SEMICONDUCTOR SCIENCE AND TECHNOLOGY, vol.35 No.11, 2020심원보
◾ Investigation of Read Disturb and Bipolar Read Scheme on Multilevel RRAM-Based Deep Learning Inference Engine, IEEE TRANSACTIONS ON ELECTRON DEVICES, vol.67 No.6 pp.2318~2323, 2020심원보
◾ Drain-erase scheme in ferroelectric field effect transistor-Part II: 3D-NAND architecture for in-memory computing, Transactions on Electron Devices, vol.67 No.3 pp.962~967, 2020심원보
◾ Drain-erase scheme in ferroelectric field effect transistor – Part I: device characterization, Transactions on Electron Devices, vol.67 No.3 pp.955~961, 2020심원보
◾ Improvement of Characteristics with a Sub-5 nm Ge-Doped Silicon Nitride Layer in Charge Trap Flash Memory Cells, Nanoscience and Nanotechnology Letters, vol.8 No.7 pp.577~580, 2016심원보
◾ Effects of Gate/Blocking oxide energy barrier on memory characteristics in charge trap flash memory cells, Nanoscience and Nanotechnology Letters, vol.7 No.7 pp.594~598, 2015심원보
◾ Gated twin-bit silicon–oxide–nitride–oxide–silicon NAND flash memory for high-density nonvolatile memory, Japanese Journal of Applied Physics, vol.54 No.6 pp.0642011~0642015, 2015심원보
◾ Stacked Gated Twin-Bit (SGTB) SONOS Memory Device for High-Density Flash Memory, IEEE TRANSACTIONS ON NANOTECHNOLOGY, vol.11 pp.307~313, 2012심원보
◾ Single-Crystalline Si STacked ARray (STAR) NAND flash memory, Transactions on Electron Devices, vol.58 No.4 pp.1006~1014, 2011심원보
◾ A Charge Trap Folded NAND Flash Memory Device With Band-Gap-Engineered Storage Node, Transactions on Electron Devices, vol.58 No.2 pp.288~295, 2011심원보
◾ Chan-Gi Yook, Wonbo Shim, Low Power Design Method of Split-Gate NOR Flash Memory Device for Compute-in-Memory, 23rd International Conference on Electronics, Information, and Communication (ICEIC 2024), Taipei, 2024심원보
◾ Do Hyun Kim, Hui-Jae Choi, Wonbo Shim, A Novel Refresh Technique for Capacitor-less DRAM-based Processing-in-Memory, 23rd International Conference on Electronics, Information, and Communication (ICEIC 2024), Taipei, 2024심원보
◾ 육찬기, 이승원, 심원보, Low-Power Split-Gate NOR Flash Cell Design and Non-Ideality Analysis for Compute-in-Memory, 31회 한국반도체학술대회, 경주, 2024심원보
◾ 공성환, 최희재, 육찬기, 심원보, A Novel 2T0C DRAM Cell Structure and Refresh Technique for Processing-in-memory Applications, 31회 한국반도체학술대회, 경주, 2024심원보
◾ 심원보, Leveraging 3D NAND Flash in processing-in-memory for hyper-scale AI models, Nano Convergence Conference 2024, 대전, 2024심원보
◾ 김도현, 전창원, 심원보, 채널 홀 형태의 편차가 3D 낸드 플래시의 Erase 동작에 미치는 영향, 대한전자공학회 추계학술대회 2023, 서울대학교, 2023심원보
◾ 이승원, 육찬기, 심원보, 온도에 따른 Split Gate NOR Flash Retention 특성과 On current 분석, 대한전자공학회 추계학술대회 2023, 서울대학교, 2023심원보
◾ 공성환, 심원보, 65 nm CMOS 2T0C DRAM 기반 Processing-in-memory, 대한전자공학회 하계학술대회 2023, 제주, 2023심원보
◾ 최희재, 심원보, Refresh 회로 구현에 따른 2T DRAM-based PIM Chip 면적 분석, 대한전자공학회 하계학술대회 2023, 제주, 2023심원보
◾ Seong Hwan Kong, Wonbo Shim, Effect of Pre-charge Voltage on Retention Characteristics and Accuracy in 65 nm 2T0C DRAM based Compute-In-Memory, ITC-CSCC 2023, Jeju, 2023심원보
◾ Wonbo Shim, Compute-in-memory Technology for Huge AI Models, ITC-CSCC 2023, Jeju, 2023심원보
◾ Chan-Gi Yook, Wonbo Shim, Refresh Methods and Accuracy Evaluation for 2T0C DRAM based Processing-in-memory, ITC-CSCC 2023, Jeju, 2023심원보
◾ Wonbo Shim, Compute-in-memory (CIM) for AI Applications based on Nonvolatile Memory Devices, IEEE NEMS 2023, Jeju, 2023심원보
◾ Wonbo Shim, 3D NAND based Compute-in-memory Technology for Energy-efficient Processing of Huge AI Models, The 17th ROK-USA Forum on Nanotechnology, The plaza Seoul, 2023심원보
◾ 육찬기, 심원보, 2T DRAM 기반 Processing-In-Memory 시뮬레이션 프레임워크 개발 및 Refresh 방법에 따른 추론 정확도 평가, 2022 대한전자공학회 추계학술대회, 광주, 2022심원보
◾ 심원보, DRAM 기반 인 메모리 컴퓨팅 시스템의 벤치마킹 프레임워크 개발, 2022 대한전자공학회 추계학술대회, 광주, 2022심원보
◾ Wonbo Shim, Nonvolatile Memory based Compute-in-memory (CIM) Technology, 2022 Asia-Pacific Workshop on Fundamentals and Applications of Advanced Semiconductor Devices, Busan, 2022심원보
◾ 구현호, 심원보, NeuroSim을 이용한 RRAM기반 Compute-in-memory 시스템의 On Resistance에 따른 Hardware spec 분석, 2022 대한전자공학회 하계학술대회, 제주, 2022심원보
◾ 최민기, 심원보, DNN+NeuroSim을 활용한 SRAM-based PIM 최적화, 2022 대한전자공학회 하계학술대회, 제주, 2022심원보
◾ 차승원, 심원보, NeuroSim을 이용한 Synaptic Array Size 변화에 따른 Computing-In-Memory(CIM) Performance Spec 평가, 2022 대한전자공학회 하계학술대회, 제주, 2022심원보
◾ 허고은, 심원보, DNN NeuroSim을 활용한 RRAM 기반 Computing-inMemory (CIM) 시스템의 Accuracy 연구, 2022 대한전자공학회 하계학술대회, 제주, 2022심원보
◾ Jian Meng, Injune Yeo, Wonbo Shim, Li Yang, Deliang Fan, Shimeng Yu, Jae-sun Seo, Sparse and Robust RRAM-based Efficient In-memory Computing for DNN Inference, 2022 IEEE International Reliability Physics Symposium (IRPS), Dallas, Texas, 2022심원보
◾ 심원보, Nonvolatile Memory based Compute-in-memory (CIM) Technology for Energy Efficient Deep Neural Network Accelerator, 제 29회 한국반도체학술대회, 강원하이원그랜드호텔, 2022심원보
◾ 공성환, 심원보, Multilevel RRAM에서의 Array Size와 Read Voltage에따른 Read Disturb의영향, 2021 대한전자공학회 추계학술대회, 인천, 2021심원보
◾ 구현호, 심원보, Multilevel RRAM의온도와시간에따른 Retention 특성연구, 2021 대한전자공학회 추계학술대회, 인천, 2021심원보
◾ Shimeng Yu, Wonbo Shim, Jae Hur, Yuan-Chun Luo, Gihun Choe, Wantong Li, Anni Lu, Xiaochen Peng, Compute-in-memory: from device innovation to 3D system integration, 2021 European Solid-State Device Research Conference (ESSDERC), Grenoble, 2021심원보
◾ Jae Hur, Yuan-Chun Luo, Zheng Wang, Wonbo Shim,Asif Islam Khan, Shimeng Yu, A Technology Path for Scaling Embedded FeRAM to 28nm with 2T1C Structure, 2021 IEEE International Memory Workshop (IMW), Dresden, Germany, 2021심원보
◾ Wangxin He, Wonbo Shim, Shihui Yin, Xiaoyu Sun, Deliang Fan, Shimeng Yu, Jae-sun Seo, Characterization and mitigation of relaxation effects on multi-level RRAM based in-memory computing, 2021 IEEE International Reliability Physics Symposium (IRPS), Virtual, 2021심원보
◾ Wonbo Shim, Jian Meng, Xiaochen Peng, Jae-sun Seo, Shimeng Yu, Impact of multilevel retention characteristics on RRAM based DNN inference engine, 2021 IEEE International Reliability Physics Symposium (IRPS), Virtual, 2021심원보
◾ Xiaochen Peng, Wriddhi Chakraborty, Ankit Kaul, Wonbo Shim, Muhannad S Bakir, Suman Datta, Shimeng Yu, Benchmarking monolithic 3D integration for compute-in-memory accelerators: overcoming ADC bottlenecks and maintaining scalability to 7nm or beyond, 2020 IEEE International Electron Devices Meeting, San Francisco, CA, USA, 2020심원보
◾ Wonbo Shim, Hongwu Jiang, Xiaochen Peng, Shimeng Yu, Architectural design of 3D NAND Flash based compute-in-memory for inference engine, 2020 ACM/IEEE International Symposium on Memory Systems, Washington DC, USA, 2020심원보
◾ Gihun Choe, Wonbo Shim, Jae Hur, Asif Islam Khan, Shimeng Yu, Impact of Random Phase Distribution in 3D Vertical NAND Architecture of Ferroelectric Transistors on In-Memory Computing, 2020 International Conference on Simulation of Semiconductor Processes and Devices, Kobe, Japan, 2020심원보
◾ Wonbo Shim, Yandong Luo, Jae-sun Seo, Shimeng Yu, Impact of read disturb on multilevel RRAM based inference engine: experiments and model prediction, 2020 IEEE International Reliability Physics Symposium, Dallas, TX, USA, 2020심원보
◾ Won Bo Shim, Seunghyun Kim, Yoon Kim, Se Hwan Park, Sungjun Kim, Euyhwan Park, Byung-Gook Park, Bitline separated gated multi-bit (BS-GMB) SONOS for high density flash memory, 2012 12th IEEE International Conference on Nanotechnology, Birmingham, UK, 2012심원보
◾ Semiconductor memory device including parallel structures, 특허 등록, 미국, 11,011,208, 2021심원보
◾ METHOD OF ERASING DATA IN NONVOLATILE MEMORY DEVICE, NONVOLATILE MEMORY DEVICE PERFORMING THE SAME AND MEMORY SYSTEM INCLUDING THE SAME, 특허 등록, 미국, 10,825,532, 2020심원보
◾ Three-dimensional memory device having a plurality vertical channel structures, 특허 등록, 미국, 10,680,013, 2020심원보
◾ Nonvolatile memory device and program method of the same, 특허 등록, 미국, 10,424,381, 2019심원보
◾ Memory device, memory system, method of operating the memory device, and method of operating the memory system, 특허 등록, 미국, 9,824,765, 2017심원보
◾ Method of detecting erase fail word-line in non-volatile memory device, 특허 등록, 미국, 9,704,596, 2017심원보
◾ Nonvolatile memory device, erase method thereof and memory system including the same, 특허 등록, 미국, 9,514,828, 2016심원보
◾ 3D stacked array having cut-off gate line and fabrication method thereof, 특허 등록, 미국, 8,786,004, 2014심원보
◾ 기둥형 단결정 채널 및 가상 소스/드레인을 갖는 낸드 플래시 메모리 어레이 및 그 제조방법(NAND FLASH MEMORY ARRAY HAVING PILLAR TYPE SINGLE CRYSTAL CHANNEL AND VIRTUAL SOURCE/DRAIN AND FABRICATION METHOD OF THE SAME), 특허 등록, 대한민국, 10-2009-0094928, 2009심원보
◾ 수직 적층구조를 갖는 앤드형 플래시 메모리 어레이와 그제작방법 및 동작방법, 특허 등록, 대한민국, 10-2008-0044005, 2008심원보
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